CV
Moldir Azhimukhanbet
Summary
BS in Computer Science at Nazarbayev University (Class of 2026), RTL Design & Verification Engineer at Texer.AI, interested in computer architecture, hardware design, and AI/ML systems.
Education
- B.S. in Computer Science — CGPA 3.68/4.0 (Top 3% of cohort)2026Nazarbayev UniversityCourses: Micro-architecture Design and Verification, Computer Systems and Organization, Operating Systems, Computer Networks, Internet of Things, Micro-controllers, Data Structures and Algorithms
Work Experience
- RTL Design and Verification Engineer2024-09 -Designing and verifying a custom 16-bit processor and tooling around it, with FPGA-based validation and verification infrastructure.
- Implemented a 16-bit 'Bitty' processor with a custom 21-instruction ISA in synthesizable Verilog, translating architectural specification to RTL.
- Designed an assembly-to-assembly translator from RISC-V32E to the custom 16-bit ISA, achieving ~95% code density while preserving functional correctness.
- Validated the processor for tapeout by implementing UART and Load-Store Unit on a DE1-SoC FPGA, achieving 140 MHz operation in 526 ALMs.
- Implemented an I²C Master for Tang Nano 9K to SSD1306 OLED communication with a memory-mapped frame buffer for real-time visualization of processor state.
- UGRIP Research Intern2025-06 - 2025-10Researched LLM-based assembly transpilation across x86, ARMv8, and RISC-V, focusing on robustness and cross-ISA correctness.
- Analyzed 200+ programs across x86, ARMv8, and RISC-V to identify systematic weaknesses in instruction semantics preservation and register allocation.
- Established a taxonomy of 25 recurring failure patterns in instruction semantics, operand encoding, and control flow.
- Designed a synthetic program generation pipeline that produced 400k C programs compiling to diverse assembly patterns, improving transpiler accuracy by ~8% on held-out cross-ISA benchmarks.
- Teaching Assistant & Lab Developer – Microarchitecture Design and Verification2025-01 - 2025-05TA and lab developer for Kazakhstan’s first hardware design course on microarchitecture and verification.
- Supported 18 students in completing working processor designs as part of the course.
- Developed UART and Load-Store Unit lab modules for DE1-SoC FPGA and mentored 20+ students in RTL debugging.
- Created a cocotb-based verification framework for Tiny Tapeout submissions, reducing onboarding time by ~70%.
Skills
Hardware Design & Verification
- SystemVerilog
- Verilog
- cocotb
- Verilator
- Icarus Verilog
- GTKWave
- FPGA
- DE1-SoC
- Tang Nano 9K
- UART
- I²C
- Wishbone
Programming
- C
- C++
- Python
Tools & Platforms
- Linux
- Git
- GitHub
- Quartus
- Gowin EDA
- Make
- Hugging Face
- vLLM
Publications
- Spaghetti-O: O2 Optimization Level CISC to RISC Transpilation2026Under submission (2026). Co-authored work on improving robustness and correctness of CISC-to-RISC transpilation at the -O2 optimization level.
Teaching
- Microarchitecture Design and Verification2025MAVERIC Lab, Nazarbayev UniversityRole: Teaching Assistant & Lab DeveloperDeveloped UART and Load-Store Unit FPGA labs on DE1-SoC, mentored 20+ students in RTL debugging, and supported 18 students in completing working processor designs.
Portfolio
- Custom 16-bit Processor & Teaching LabsHardware & teachingBitty 16-bit processor with custom 21-instruction ISA, RISC-V32E→Bitty asm-to-asm translator, Tiny Tapeout integration, and FPGA-based microarchitecture teaching labs.
Interests
- Computer Architecture & MicroarchitectureCustom ISAs, Processor design, Verification
- ML for Systems & Systems for MLLLM-based program translation, Compiler-aware ML, Robustness
- Edge AI & Educational SystemsSTT–LLM–TTS pipelines, Resource-constrained deployment, Language learning systems